1. Field of the Invention
This disclosure generally relates to techniques for reducing cache miss delays for processors in computer systems. More specifically, this disclosure relates to techniques for simultaneously sending speculative memory access requests to lower levels of a multi-level memory hierarchy during a cache access.
2. Related Art
To achieve high instruction throughput rates, the memory subsystem of a processor typically includes multiple levels of cache memories. Accesses to such cache memories generally operate as follows. During execution, a processor may execute a program instruction that references a memory location. If the referenced memory location is not available in a level one (L1) cache, a cache miss causes the L1 cache to send a corresponding request to a level two (L2) cache. Next, if the referenced memory location is also not available in the L2 cache, additional requests may need to be sent to lower levels of the processor's memory hierarchy.
Unfortunately, while caching techniques generally improve memory access speeds, such sequential misses to both the L1 and L2 caches are sometimes unavoidable. Furthermore, serially handling a set of sequential misses for multiple levels of a memory hierarchy can lead to a substantial combined miss delay. Hence, what is needed are techniques for accessing caches efficiently without the above-described problems.